Reconfiguration Management in the Context of RTOS-Based HW/SW Embedded Systems
نویسندگان
چکیده
HW/SW interface for an embedded system-on-chip is an important topic. It allows communications between tasks independently of their implementations. In our adaptive strategy, communications are not limited to data since local data (task context: recursive data, counters), configuration (pointers, configuration ID), and metrics are also exchanged. Thus, task communications are encapsulated within a unified interface called UCCI (see Figure 1) that handles configuration, data, and control communications in such a way that usual SW and HW implementations can be directly instantiated in the new framework. Each HW task has a legal representative (LR) which is a lightweight SW task that maintains communications between RTOS and tasks implemented in hardware. Local data can be read (resp., written) by the LR in case of HW to SW (resp., SW to HW) migration or by the HW UCCI in case of HW to HW migration. Basically, a context transfer is equivalent to a data transfer performed between reconfigurations in case of HW to SW or HW to HW migrations. The UCCI implementation imposes some constraints regarding I/O format. For instance, local data are based on identical stacks for all HW and SW versions. Moreover, some SW routines have been added for data format adaptation; the more used one is the bit/byte conversion routine required when SW tasks accede to binary images where pixel is coded as bit for bandwidth and area optimization. 2.2.2. Tasks communication Communications with an SW task are involved to call the intertask communication RTOS services. Two kinds of operation can be used: post and pend communications. For SW → SW communications, traditional communication services are used, whereas in HW ↔ SW communications, the LR task Y. Eustache and J.-P. Diguet 3 Architecture configuration Dataflow configuration
منابع مشابه
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems
A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its ...
متن کاملDynamic Hw Priority Queue Based Schedulers for Embedded System
A real-time operating system (RTOs) is often used in embedded system, to structure the application code and to ensure that the deadlines are met by reacting on events by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. RTOs are generally implemented in software, increases computational overh...
متن کاملSystematic Embedded Software Generation from SystemC
The embedded software design cost represents an important percentage of the embedded-system development costs [1]. This paper presents a method for systematic embedded software generation that reduces the software generation cost in a platform-based HW/SW codesign methodology for embedded systems based on SystemC. The goal is that the same SystemC code allows system-level specification and veri...
متن کاملSoftware and Driver Synthesis from Transaction Level Models
This work presents a method of automatically generating embedded software including bus driver code from a transaction level model (TLM). For the application software, a real time operating system (RTOS) adapter is introduced to model scheduling and synchronization at C level. ANSI-C code is generated targeting this RTOS adapter. Bus drivers are also automatically created for HW/SW communicatio...
متن کاملEmbedded Architecture Description Language
In the state-of-the-art hardware/software (HW/SW) codesign of embedded systems, there lacks of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ought to capture both hardware and software components and their interactions, and facilitate effective design exploitation of HW/SW trade-offs and scalable HW/SW co-verification. In this p...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- EURASIP J. Emb. Sys.
دوره 2008 شماره
صفحات -
تاریخ انتشار 2008